1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems utilising coherent memory management in which multiple copies of data may be stored in different memories within the system under control of coherency management mechanisms enforcing a required degree of coherence between the different copies of the same data.
2. Description of the Prior Art
It is known to provide data processing systems in which multiple copies of data values may be held at different points within the data processing system. For example, a system including multiple processors may have a local cache memory associated with each of these processors. The multiple processors may all be connected to a shared main memory. The local cache memories may hold a copy of data held within the main memory and it is possible for multiple cache memories to hold copies of the same data. Within such systems it is important that coherence between the multiple data values should be maintained such that, if it is required, an individual processor sees the most up-to-date version of a data value and should a data value be changed within one of the cache memories, then that updated data value is ultimately written back to the main memory. There are many known mechanisms for controlling the coherence and data access ordering between the different data values depending upon the requirements of the system.
One ordering management technique employs fence instructions (ordering instructions) within the stream of program instructions executed by a processor. Such fence instructions have the behaviour that they are not committed until all memory accesses preceding the fence instruction within the program stream have been completed. Another approach to ordering management is to ensure sequential consistency using, for example, a variety of micro-architectural techniques such that all memory access operations give results corresponding to the memory access operations being performed in the order in which they are located within the stream of program instructions being executed. While these techniques ensure a degree of coherence as desired, they can impose performance constraints in some circumstances. As an example, if a store operation is to be performed and the data concerned is not already cached within the local cache of the processor performing the store operation, then that data may require fetching from the main memory to the local cache memory of the processor concerned before the store operation may be completed. The latency associated with this fetch of the data from the main memory may be considerable. If a fence instruction is preventing processing proceeding further until a preceding stalled store instruction is completed, then a considerable loss in performance will arise. However, the fence instruction in this circumstance does ensure that the preceding store operation is completed as intended before processing subsequent to the fence instruction is permitted.